Transports & Buses
Everything a host BMC or peer device sends to the controller arrives over a bus and (usually) an MCTP transport. This section covers the transport core and the physical bus drivers.
- MCTP transport — the base Management Component Transport Protocol layer, plus inter-core IPC and the mailbox. (deep-dive)
- Bus drivers — I2C, I3C, SPI, UART, USB, and the SSIF SMBus interface. (catalog)
| Subsystem | Path | Role |
|---|---|---|
| MCTP | src/nv/mctp/ |
Transport core / binding / composer |
| IPC | src/nv/ipc/ |
Inter-core (core0↔core1) messaging |
| Mailbox | src/nv/mainbox/ |
Mailbox primitive |
| I2C | src/nv/i2c/ |
I2C controller/target, EEPROM cache |
| I3C | src/nv/i3c/ |
I3C (GPU-facing) |
| SPI | src/nv/spi/ |
External flash access |
| UART | src/nv/uart/ |
Serial |
| USB | src/nv/usb/, src/nv/usb_proxy/ |
HID/SMBus over USB |
| SSIF | src/nv/ssif/ |
SMBus System Interface (IPMI-style) |
| VCOM | src/nv/vcom/ |
Virtual COM |