NHP & LSTP messaging
Beyond the DMTF stacks (PLDM, SPDM), OpenSMA carries a few smaller, NVIDIA-specific messaging paths. This page is a catalog: each gets a short subsection covering its role and key files.
NHP — E.1S hot-swap handler
src/nv/nhp/ implements the drive-bay hot-swap handler. The controller
presents itself to a host as a bank of PCA9555 GPIO expanders over an
I2C-slave interface; the host reads/writes a 16-bit control register per
E.1S drive to drive PERST#, clock enable, power enable/disable, and the
amber/blue status LEDs.
NHPclass (src/nv/nhp/nhp.h:44) owns the per-drive I2C-slave driver, GPIO-expander emulators, and the hot-swap state machines. The I2C-slave driver dispatches transactions toNHP::i2c_callback(src/nv/nhp/nhp.cpp:140), which routes register reads/writes to the right drive index.- Hot-swap state machine —
NhpE1sHotSwap(src/nv/nhp/hssm.h:26) tracksDriveDisabled/HostControl/PowerFaultper drive.update_control_register(src/nv/nhp/hssm.cpp:42) applies the host’s 16-bit pin-control vector onto the physical GPIO pins. - Register bit map — the control-register bit assignments (PERST#,
clock-enable, present, LEDs, power-enable/disable, power-good) are
defined in
src/nv/nhp/common.h:64. - Task —
nv::nhp::Task(src/nv/nhp/task.h) runs an ADC polling loop for 12 V power-good monitoring (src/nv/nhp/task.cpp:66) and forwards GPIO / ADC interrupts into theNHPinstances.
Interpretation: NHP is a GPIO/power-sequencing protocol for E.1S NVMe bays rather than a message-transport like MCTP; the “protocol” is the PCA9555 register layout the host drives over I2C.
LSTP — channel-multiplexed request/response
LSTP is a lightweight request/response protocol that multiplexes several
logical channels (management, SPI, GPIO, I2C, UART, IPMI) over a
single link — primarily USB. It is split into a shared parser
(src/nv/lstp/) and a bare-metal router (src/nv/lstp_bm/).
- Wire format — every message starts with a 4-byte
LstpHdr(src/nv/lstp/lstp_common.h:146):channel_id,cmd_status_code(bit 7 flags request vs. response,LstpResponseBit), and a 16-bit length. Channel types are enumerated atsrc/nv/lstp/lstp_common.h:63and status codes atsrc/nv/lstp/lstp_common.h:84; the max message size is 512 bytes. - Parser —
LstpParser(src/nv/lstp/lstp_parser.h:27) is transport-agnostic.validate_request(src/nv/lstp/lstp_parser.cpp:24) bounds-checks the header/length,parse_channel_type(src/nv/lstp/lstp_parser.cpp:53) resolves the configured channel (including the flashrom channel-0 SPI alias), andparse_spi_request(src/nv/lstp/lstp_parser.cpp:80) decodes SPI read/write/write-read commands. - Bare-metal router —
nv::lstp::bm::LstpRouter(src/nv/lstp_bm/lstp_router.h:27) runs inside the USB stack.receive(src/nv/lstp_bm/lstp_router.cpp:31) switches on the parsed channel type and forwards toreceive_spi(which drives the bare-metalSpiManager) orreceive_i2c;send_error(src/nv/lstp_bm/lstp_router.cpp:55) andsend_spiwrite responses back into the USB LSTP TX buffers. - RTOS-side router / task — a fuller
LstpRouter(src/nv/lstp/lstp_router.h:59) handles the remaining channel types, andLstpTask(src/nv/lstp/lstp_task.h:60) provides the event-driven GPIO channel (submit_gpio_req/submit_gpio_irq).
IPC handler — inter-task dispatch
src/nv/ipchandler/ is the small router that moves a message from one
task to another task’s queue. It is the mechanism PLDM and SPDM use to
exchange firmware-authentication requests and results without sharing
state.
- Endpoints —
nv::ipchandler::Id(src/nv/ipchandler/enums.h:30) enumerates the addressable tasks/queues:Mctp,I2c0–I2c9,I3c0/I3c1,Pldm,Usb,Flash,Logger,Spdm,Iox,Lstp. - Driver —
Driver::send(src/nv/ipchandler/ipchandler.cpp:26) wraps the payload in aHeader(src/nv/ipchandler/ipchandler.h:27— source/dest id, size, request flag) and callsDriver::handler(src/nv/ipchandler/ipchandler.cpp:53), which switches ondst_idand forwards to the matching I3C / I2C / USB / PLDM queue. - Callers — the PLDM task’s
Task::to_pldmand the SPDM→PLDM authentication-result path both go through this handler (see PLDM).
Where to look next
- The transports these protocols ride on: Transports & Buses and the MCTP transport deep-dive.
- Overall task/queue model: Architecture.
- Back to the section overview: Management Protocols.